1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, particularly relates to a word line selecting circuit of normal memory cell/spare memory cell for an array of memory cells, in which a ferroelectric capacitor is used, and the circuit used for, e.g. a ferroelectric memory integrated circuit.
2. Description of the Related Art
Recently the ferromagnetic memory (FeRAM) having an array of memory cells in which the ferroelectric capacitor is used receives much attention as one of nonvolatile memories. FeRAM has advantages such that rewritability is the order of 1012, read/write cycles are comparable to DRAM, and operation voltage is low-voltage of 2.5 to 5V.
FIG. 9 shows a part of an array of FeRAM cells having one transistor/one capacitor configuration. This cell array is the same as that of DRAM except the configuration of the cell itself is different from that of DRAM.
In FIG. 9, the normal memory cell and the spare memory cell for storing information includes a ferroelectric capacitor 7 having a structure in which a ferroelectric film is sandwiched between two electrodes, and a transistor (selecting transistor) 8 for selecting the cell, the normal memory cell and the spare memory cell are connected to the same bit line BL.
One electrode of the ferroelectric capacitor 7 of the normal memory cell is connected to a plate line PL, and the other electrode of the ferroelectric capacitor 7 of the normal memory cell is connected to a bit line BL via a selecting transistor 8. A gate of the selecting transistor 8 of the normal memory cell is connected to a normal word line WL.
One electrode of the ferroelectric capacitor 7 of the sparel memory cell is connected to a spare plate line SPL, and the other electrode of the ferroelectric capacitor 7 of the spare memory cell is connected to the bit line BL via a selecting transistor 8. A gate of the selecting transistor 8 of the spare memory cell is connected to a spare word line SWL.
FIG. 10 shows a part of the array of TC-parallel-unit series connection type of ferroelectric memory cells. The configuration of the TC-parallel-unit series connection type of ferroelectric memory cell is described in Jpn. Pat. Appln. KOKAI Publication No. 10-255483 applied by the applicant.
That is, in FIG. 10, the normal memory cell and the spare memory cell have the configuration in which a plurality of cell units, in which the ferroelectric capacitors 7 are connected in parallel between a source and a drain of the cell transistor 8, are connected in series (TC-parallel-unit series connection type of ferroelectric memory cell).
In this case, one terminal of the normal memory cell is connected to a plate line PL, the other terminal of the normal memory cell is connected to the bit line BL through a block selecting transistor 9, the gate of the block selecting transistor 9 is connected to a block selecting line BS, and the gate of each selecting transistor 8 is correspondingly connected to an individual word line WL.
On the other hand, one terminal of the spare memory cell is connected to a spare plate line SPL, the other terminal of the spare memory cell is connected to the bit line BL through the block selecting transistor 9, the gate of the block selecting transistor 9 is connected to a spare block selecting line SBS, and the gate of each selecting transistor 8 is correspondingly connected to an individual spare word line SWL.
FIG. 24 is a block diagram showing a part of the conventional example of a circuit of a word line selecting system and the cell array in FeRAM having the cell array shown in FIG. 9.
An address input circuit 91 has a function of waveform-shaping an inputted address signal.
A substitution requirement judging circuit 92 stores an address, e.g. in a fuse element in substituting the normal memory cell for the spare memory cell, compares an input address supplied from the address input circuit 91 with the stored address to judge whether the substitution is required or not, and drives a normal word line driver 93 or a spare word line driver 94 according to the judgment result.
Drive output of the normal word line drivers 93 is supplied to the normal word line WL connected to the normal memory cell of a normal cell array 95, and the drive output of the spare word line drivers 94 is supplied to the spare word line SWL connected to the spare memory cell of a spare cell array 96.
Though it is not shown, a normal plate line driver for driving the normal plate line PL connected to the normal memory cell and a spare plate line driver for driving the spare plate line SPL connected to the spare memory cell are provided.
FIG. 25 is a waveform chart showing an operation example in the case where the spare word line SWL is selected by using the circuit of the word line selecting system of the conventional example shown in FIG. 24 in the array of FeRAM cells having the one transistor/one capacitor configuration, which is shown in FIG. 9.
The address signal is inputted at time t1 and the substitution requirement judging circuit 2 judges (fuse-judges) at time t2 that the substitution is required by comparing the input address with the address stored in the fuse element. As a result, potentials of the normal word line WL and the normal plate line PL, which have not been selected, are fixed to an “L” level respectively, and read/write operation of the memory cell is not carried out.
On the contrary, the read/write operation of the spare memory cell is carried out in such a manner that the selected spare word line SWL is driven to an “H” level and then the spare plate line SPL is driven to the “H” level.
FIG. 26 is a waveform chart showing an operation example in the case where the spare word line SWL is selected by using the circuit of the word line selecting system and the cell array of the conventional example shown in FeRAM having the array of the TC-parallel-unit series connection type of ferroelectric memory cells shown in FIG. 10.
When the address signal is inputted at time t1 and the judgment is carried out at time t2 by the substitution requirement judging circuit 2, the potential of the normal word line WL which has not been selected is fixed to the “H” level, the potentials of the normal plate line PL and the block selecting line BS which have not been selected are fixed to the “L” level, and read/write operation of the memory cell is not carried out.
On the contrary, the read/write operation of the spare memory cell is carried out in such a manner that the selected spare word line SWL is driven to the “L” level, and then the block selecting line BS is driven to the “H” level to connect the spare memory cell to the bit line BL, and the spare plate line SPL is driven to the “H” level.
However, in the circuit of the word line selecting system of the conventional example shown in FIG. 24, after the address signal is inputted to the address input circuit 1, according to the result of comparison of the input address and the stored address in the substitution requirement judging circuit 2, it is judged whether the normal word line WL for the normal memory cell of the normal cell array 5 or the spare word line SWL for the spare memory cell of the spare cell array 6 is selected, so that delay of access time is generated.
As described above, there is a problem that the access time is lengthened in the word line selecting circuit of the conventional FeRAM.